Flash architecture

Stacking up the memory cells so that each of them stores 2 or 3 bits of information is called a multilevel cell or MLC. SanDisk and Toshiba will jointly instigate the world’s first 16GB 3bits per cell flash chip. These chips use the NAND flash architecture. This indicates that flash cells are linked in series that reminds you of the NAND gate. Limitation involved is that NAND flash reading speeds are less compared to the NOR but we have better writing speed here.

In Phase change memory technique the microscopic bit is excited to about 600 degree Celsius. This process melts the bit which when cooled coagulates into one of the two crystalline structures, which represent a binary one or zero. Users can protract tens of millions as a replacement for tens of thousands of read-write cycles compared to NAND flash. This allows dwindling the manufacturing tolerance to 45nm, which means squeezing more and more cells on every square centimeter of substrate till a gigabyte will trim down to a dot.